Low frequency, or 1/f noise has long been a concern in the implementation of high performance analog transistor technology. It is generally accepted that 1/f noise is caused by carriers, such as electrons or holes, being transiently trapped in the gate dielectric or the interface between the gate dielectric and the channel of a transistor. The random translocation of carriers into traps or defect centers, such as silicon dangling bonds, into the gate dielectric and back into the channel, causes the current through the transistor to fluctuate, which manifests as 1/f noise.
The push toward smaller and faster semiconductor devices has increased the need to reduce 1/f noise. As an example, it is well known that the output noise spectrum (Sids) of 1/f noise from a transistor device increases as an inverse second order function of decreasing effective channel length (i.e., Sids∝1/Leff2). The increase in 1/f as device area is decreased has especially deleterious consequences for analog-to-digital converter and amplifier applications.
The effect of 1/f noise can be partially mitigated by using transistors having large device areas in the initial stages so that 1/f noise does not get amplified to the same extent as the signal in subsequent stages of an amplification circuit. This approach, however, does not prevent 1/f noise from being introduced at later amplification stages in the circuit where smaller transistors are used. Moreover, the dimensions to which such devices can be scaled down to are limited by the necessity for one or more large early stage transistors.
Accordingly, what is needed in the art is a method of making transistor devices having reduced 1/f noise that can be inexpensively incorporated into very large scale integration systems (VLSI) that do not exhibit the limitations of the prior art.